Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - memory vhdl

Search list

[VHDL-FPGA-Verilog] 6FloorLift

Description: 设计一个6层电梯控制器。电梯控制器是按照乘客的要求自动上、下的装置。 1、每层电梯入口处设置上下请求开关，电梯内设有顾客到达层次的停站请求开关。 2、设有电梯所处位置指示装置以及电梯运行模式（上升或者下降）指示装置。 3、电梯每秒升降一层楼。 4、电梯到达有停站请求的楼层，经过1秒电梯门打开，开门4秒后，电梯门关闭（开门指示灯灭），电梯继续运行，直至执行完最后一个请求信号后停留在当前层。 5、电梯能记忆电梯内外所有请求信号，并按照电梯运行规则按顺序响应，每个请求信号保留至有电梯响应后消除。 6、初始状态为一层开门，第一层不用向下开关，最高层不用向上开关。 7、电梯运行规则：当电梯上升时，只响应比电梯所在位置高的上楼请求信号，由下而上逐个执行，直到最后一个上楼请求执行完毕；如果高层有下楼请求，则直接升到下楼请求的最高楼层，然后进入下降模式。当电梯处于下降模式时与上升正好相反。 -design of a six-story elevator controller. Elevator Controller in accordance with the requirements of passengers automatically, the device. 1, installed on each floor elevator entrance next request switches, elevator begins to reach the level of customer stops request switch. 2, the location of elevator and escalator installations instructions operation mode (up or down) device instructions. 3, Elevator per second floor landing. 4, the lift reached a request stops floors seconds after an elevator doors open door four seconds later, elevator doors closed (to open the door to eliminate light), the continued operation of the lift, End until the implementation of the final request for a signal to stay in the current layer. 5, the lift will lift internal and external memory signal to all reques
Platform: | Size: 2048 | Author: zheng | Hits:

[VHDL-FPGA-Verilog] S3Demo

Description: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
Platform: | Size: 731136 | Author: Roy Hsu | Hits:

[File Format] designforvideobasedonSDRAM

Description: 在信息处理中，特别是实时视频图像处理中，通常都要对实现视频图像进行处理，而这首先必须设计大容量的存储器，同步动态随机存储器SDRAM虽然有价格低廉、容量大等优点，但因SDRAM的控制结构复杂，常用的方法是设计SDRAM通用控制器，这使得很多人不得不放弃使用SDRAM而使用价格昂贵的SRAM。为此，笔者在研究有关文献的基础上，根据具体情况提出一种独特的方法，实现了对SDRAM的控制，并通过利用FPGA控制数据存取的顺序来实现对数字视频图像的旋转，截取、平移等实时处理。-In information processing, especially real-time video image processing usually have to deal with video images, which must first be designed large-capacity memory, synchronous dynamic random access memory SDRAM Although there are low cost, large capacity, etc., but SDRAM control structure of the complex, commonly used method is to design generic SDRAM controller, which makes a lot of people had to abandon the use of SDRAM and the use of expensive SRAM. To this end, the authors examine the literature based on the specific situation in a unique way to realize the control of SDRAM, and control data through the use of FPGA to realize the order of access to digital video image rotation, interception, translation, such as real-time processing.
Platform: | Size: 137216 | Author: 赵明玺 | Hits:

[VHDL-FPGA-Verilog] modelsim

Description: 基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft -Memory based on the base 4 by the frequency of fft taken the VHDL description of the continuous data stream can be carried out 256 point fft
Platform: | Size: 22528 | Author: 庞志勇 | Hits:

[VHDL-FPGA-Verilog] mctrl

Description: 不可多的的内存控制代码,是VHDL开发的珍贵参考资料!-Not much memory control code is developed in VHDL valuable reference!
Platform: | Size: 5120 | Author: 徐新风 | Hits:

[Other Embeded program] IIC-EEPROM

Description: 用verilog实现了IIC接口与EEPROM存储器的接口设计，非常实用-Using Verilog realize the IIC interface with the EEPROM memory interface design, very useful
Platform: | Size: 9216 | Author: zhangyanbo | Hits:

[Embeded-SCM Develop] moore

Description: Moore型状态机设计,基于VHDL.能够根据微处理器的读写周期,分别对应存储器输出写使能WE和读使能OE信号.-Moore-type state machine design, based on VHDL. Be able to read and write cycle of microprocessors, corresponding memory output enable WE write and read enable signal OE.
Platform: | Size: 25600 | Author: weixiaoyu | Hits:

[VHDL-FPGA-Verilog] my_zbt_controller

Description: ZBT内存控制器.支持OPB总线。VHDL源码-ZBT memory controller. Support the OPB bus. VHDL source
Platform: | Size: 1024 | Author: 吕奔 | Hits:

[VHDL-FPGA-Verilog] cf_vhdl

Description: CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification. -CF VHDLThe CF+ Design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification.
Platform: | Size: 700416 | Author: gbh | Hits:

[VHDL-FPGA-Verilog] EP2C5Q208

Description: 以cyclone系列的EP2C5Q208为核心的实验板程序.包括流水灯,I2C存储器.SPI存储器,数码管,串口,LCD等-Cyclone in series as the core EP2C5Q208 experimental procedure. Including water lights, I2C memory. SPI memory, digital control, serial port, LCD, etc.
Platform: | Size: 2980864 | Author: sarah | Hits:

[Other] SOPC

Description: SOPC是一种新的系统设计技术，也是一种新的软硬件综合设计技术。通过它，可以很快地将硬件系统（包括微处理器，存储器，外设以及用户逻辑电路等）和软件设计都放在一个可编程的芯片中，以达到系统的IC设计.-SOPC is a new system design technology, but also a new integrated software and hardware design techniques. Through it, can quickly create hardware systems (including microprocessors, memory, peripherals and user logic circuits, etc.) and software design on a programmable chip, in order to achieve system IC design.
Platform: | Size: 5891072 | Author: 26 | Hits:

[Software Engineering] FPGAandSDRAM

Description: 基于FPGA技术的存储器设计及其应用 原理详细！！！1-Memory-based FPGA technology design and application of the principle of detail! ! ! 1
Platform: | Size: 4096 | Author: JP | Hits:

[OS Develop] FIFO

Description: 先进先出存储器的程序，希望对初学者有所帮助。-FIFO memory of the procedure, and they hope to be helpful to beginners.
Platform: | Size: 1024 | Author: tian | Hits:

[VHDL-FPGA-Verilog] MyCPU16

Description: 16位cpu设计VHDL源码，其中包括alu，clock，memory等部分的设计-16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
Platform: | Size: 1089536 | Author: 孙冰 | Hits:

[VHDL-FPGA-Verilog] PicoBlaze

Description: 描述：LED示范、按钮及开关、视频输出、键入、含Xilinx PicoBlaze微处理器的存储器模块-Description: LED model, buttons and switches, video output, type, including Xilinx PicoBlaze microprocessor memory modules
Platform: | Size: 1721344 | Author: 陈晓 | Hits:

[VHDL-FPGA-Verilog] vhdl_180gelizi

Description: VHDL的一些实例。 有加法器。存储器之类的。基本模块-Some examples of VHDL. Have adder. Like memory. Basic modules
Platform: | Size: 112640 | Author: KKKK | Hits:

[OS Develop] FIFO

Description: fifo.v verilog实现的先进先出存储器-fifo.vverilog realize the FIFO memory
Platform: | Size: 2048 | Author: patrick | Hits:

[source in ebook] pwm

Description: 紧耦合存储比内存和cacsh都要快很多希望大家能够理解这个东西，非常好的参考，-Tightly coupled memory and storage than the much faster cacsh must hope that everyone can understand this thing, very good reference,
Platform: | Size: 362496 | Author: 李可 | Hits:

[VHDL-FPGA-Verilog] SRAM-PINGPANG

Description: 超声视频图像需要实时地采集并在处理后在显示器上重建，图像存储器就必须不断地写入数据，同时又要不断地从存储器读出数据送往后端处理和显示[11]。为了满足这种要求，可以在采集系统中设置2片容量一样的SRAM，通过乒乓读写机制来管理。任何时刻，只能有1片SRAM处于写状态，同时也只有1片SRAM处于读状态。工作期间，2片SRAM都处于读写状态轮流转换的过程，转换的过程相同，但是状态错开，从而保证数据能连续地写人和读出祯存.-Real-time ultrasound video images need to collect and deal with the reconstruction after the display, image memory must be continually write data, while at the same time continuously sent from the memory读出数据back-end processing and display [11]. To meet this requirement, you can set up collection system capacity of two different SRAM, read and write through the ping-pong mechanisms to manage. At any time, can only have a SRAM in write state, but also the only one at a time the state of SRAM. Work, two SRAM read and write are in the process of converting a state of rotation, the conversion process of the same, but the state staggered to ensure that data can be continuously written and read out Qizhen depositors.
Platform: | Size: 1024 | Author: smj1980 | Hits:

[VHDL-FPGA-Verilog] uriscram

Description: RAM存储器： 设定16 个8 位存储单元。如果read= 1 则dataout<=mem(conv_integer(address)). 如果write= 1 则mem(conv_integer(address))<=datain. -RAM memory: Set 16 8 memory cell. If read = 1 is dataout
Platform: | Size: 1024 | Author: 良芯 | Hits:
« 1 2 34 5 6 7 8 9 10 ... 14 »

CodeBus www.codebus.net